In manufacture of an integrated circuit (IC), such as large scale integrated circuits (LSI) and ultra-large scale integration (ULSI) integrated circuits, a damascene process that eliminates the demands of a metal dry etch for forming conductive wiring and a dielectric gap fill has been commonly utilized to form interconnections, responsible for intercommunications among multiple stacked metallization layers in the semiconductor device in a back-end-of-line (BEOL) fabricating stage.
A typical damascene process involves steps of etching trenches or vias in a multi-layered planar dielectric layer, and then filling the trenches or vias with metal, such as aluminum or copper. After filling, the excess metal outside the trenches is planarized and polished by chemical mechanical polishing, so that metal is only left within the trenches to form conductive interconnections transmitting electronic signals. Often, the damascene process is generally classified into three categories including a via first trench last (VFTL) scheme, a trench first via last (TFVL) scheme and a self-aligned via first (SAVF) scheme.
In such damascene process, due to the fact that various composite isolation layers, such as hard mask layers and etch stop layers, usually having a relatively lower etch rate than those of dielectric layers nearby are vertically interlaid among dielectric layers, there yields a non-uniform etch selectivity distributed along a vertical profile for the multi-layered formed damascene structure. Accordingly after etching, there unavoidably forms an uneven non-vertical sidewall in the trenches which causes an irregular trench profile, in particular an upwardly narrowing tapered trench profile having a quite narrowing pattern around the top opening for the trench. Upon filling, a filling metal may be excessively deposited on the narrowing part around the top opening for the trench easily which causes the trench to be early sealed during filling process, resulting in an issue commonly known as an necking effect, or also known as a metal gap fill limitation.
As a trend that electronic devices continue to be smaller, less expensive, and more powerful, a critical concerned issue with respect to a resistive-capacitance (R×C) delay time characteristic dominating the circuit performance in IC for the electronic devices is correspondingly raised. Accordingly, the inter-metal dielectric layer or inter-layer dielectric layer is generally made of material has a dielectric constant to be as low as possible, such as an extremely low-k (ELK) material, so as to improve the R×C delay time characteristic and to well insulate the respective metallization parts for preventing crosstalk from each other that degrades device performance by slowing circuit speed.
Nevertheless, although an ELK material is involved in, another concerned issue is that dry etch plasma can always deteriorate the deposited ELK layer by forming a thin damaged layer with a relatively higher dielectric constant along the contacting edge of the etch plasma and dielectric inside the ELK layer, which increases the entire dielectric constant and correspondingly impacts and increases the entire capacitance for the deposited ELK layer. Hence, there arises another issue that an overall R×C delay performance for the finalized semiconductor device containing the damaged ELK layer may be correspondingly affected and worsened.
With the miniaturized development for semiconductor fabricating technology for sub-micron, or even for 28 nm, 20 nm or nodes beyond semiconductor technology, it is anticipatable that there will encounter more and more difficulties in the aspect pertaining metal gap filling limitation and high Rs concern.
There is a need to solve the above deficiencies/issues.